1. Field
The embodiment of the present invention relates to a memory system.
2. Description of the Related Art
As the technologies for realizing mass-storable memory systems, memory cells of the variable resistance type, such as ReRAMs and ion memories, have received attention. These memory cells can be formed of the cross point type between selection lines and accordingly it is possible to easily construct a cell array having a three-dimensional structure.
These memory cells of the variable resistance type include ones that have asymmetrical characteristics of which voltage-current characteristic greatly changes in accordance with the direction of bias applied to the memory cell. For the cell array having the three-dimensional structure that includes the memory cells having such the asymmetrical voltage-current characteristic, an access operation of the so-called floating access method is effective. The access operation of the floating access method is referred to as an access method of providing an access-targeted selection line with a potential required to make access to a memory cell while bringing non-access selection lines into the floating state.
The cost of a memory system chip is considered here. From the viewpoint of the cost of the chip, the higher the share of the chip area by a cell array, the lower the cost required to realize a mass-storable memory system. Such the three-dimensionally structured memory cell including memory cells of the cross point type, however, generally requires peripheral circuits such as large-sized decoders and drivers. Therefore, an increase in the share of the chip area by the cell array requires the cell array to be made on a larger scale.
If the cell array is made larger, however, occurrences of faults in memory cells increase naturally. Therefore, it is important in such the memory system to handle fault memory cells.